New Release: Magillem 5.2018.4

New Release: Magillem 5.2018.4 MPA / MIP / MRV « In addition to several bug fixes on APIs, GUI, importers, RTL netlisters, and register generators, this release provides multiple enhancements for VHDL/SystemC ports defined with specific types, to facilitate their creation, […]

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Magillem takes part of the ITEA3-REVaMP2 project

Magillem takes part of the ITEA3-REVaMP² project From June 26 to June 28, 2018, Magillem is actively involved in the REVaMP² project plenary session, held in Karlsruhe (Germany), at the premises of FZI (Forschungszentrum Informatik), Research Center of Information technology. […]

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