DVCON Japan, June 30, 2017, Shin-Yokohama Kokusai Hotel, Yokohama, Kanagawa, Japan
Magillem exhibits and hosts a SystemC-track session about “Using Virtual Prototypes to Verify Functional Requirements“, at the Design and Verification Conference and Exhibition Japan – DVCON JAPAN, sponsored by Accellera Systems initiative, on June 30, 2017 at Shin-Yokohama Kukusai Hotel, Yokohama, Kanagawa.
DVCON Japan 2017 is a technical conference targeting the application of standardized languages, tools and methodologies for the design and verification of electronics systems and integrated circuits.
The Magillem team has been a contributor to the IP-XACT specification since 2003. Our proposed solution relies on a standard-based (DITA, ReqIF, SysML, IP-XACT, SystemC, C/C++) integrated environment capable of creating and managing links between heterogeneous objects, capable of executing, very early in the design cycle, both the Software and the Hardware requirements on the target Virtual Prototype to detect functional errors, and capable of tracing the impact of any change in the requirements down to the embedded system execution and vice-versa.
At DVCon Japan, Magillem hosts a SystemC –track session about “Using Virtual Prototypes to Verify Functional Requirements“, from 11:20 am to 11:50 am, held by Pascal Chauvet, Vice President – Strategic Accounts Manager.
You will learn more about how Virtual Prototypes can be used to perform an early validation of the functional requirements by creating the missing links between the different refined models that characterize a design: requirements, specification, implementation and execution.