Virtual Platforms: New trends. How MAGILLEM addresses them with MVP®
Magillem Press release – August 29th, 2017
Magillem, the leading provider of front-end design xml solutions, best-in-class tools to reduce the global cost of complex designs, announces availability of MVP, Magillem Virtual Platform, its software aiming at creating , configuring, analyzing and maintaining a Virtual Platform.
A new momentum in SystemC/Virtual Prototypes adoption is happening for three major reasons
• System companies are being more involved in the development of ASIC/FPGA through their digital transformation process: Electronic is now everywhere, and to differentiate a system, it is not enough to just assemble available IP, they need to create their own ASIC/FPGA. VP is a good solution to specify/verify their requirements, defined as an executable contract, between their various sub-teams or sub-contractors.
• Smaller Analog/MEMS Semiconductor companies, boosted by the transformed markets (e.g. Automotive) or new emerging markets (e.g. Augmented reality), look for differentiators to produce their devices sooner, better, faster. Or they are forced by their customers (the System equipment manufacturers) to provide a VP of their device. ( We address that segment with our X-Spec platform).
In addition, we see a change in the VP usage
Originally driven by the consumer market (smartphones/tablets) with tight TTM, VP were developed to speed up early software bring-up. A decade later, the VP market has changed to cover new/adapted markets such as Automotive, Medical, Aerospace, IoT…
• Mix Analog/Digital platforms (not just pure digital) including sensors, MEMS, and RF chains
• Smaller platforms (based on micro-controller)
• Many-core platforms (versus multi-core), for example to model a vehicule including hundreds of ECUs
• System heterogeneous platforms mixing, for example, SystemC and Matlab models.
Sometimes the VP may not even include a processing unit, hence not execute software.
We also see new VP usage : the VP usage is expanding to cover (in addition to software bring up):
• Hardware IP (or subsystem) validation/verification and this includes:
> Validation from embedded software, where the testbench environment includes a processor fast model, or by directly running software test patterns using the embedded processor of the SoC
> Validation using a hardware test bench (usually coupled with the previous one). The test bench is written in SystemC, generating stimuli and responding to side signals. The test bench can also be based on the UVM-SystemC
• Early system demonstrator
The VP is being more and more used as an early product demonstrator: an executable specification. This is typically used when responding to a call for tender, to illustrate how your future product can differentiate and respond to the requirements. The VP becomes a live specification, that can execute a number of user stories/use-cases, which is easy to exchange between stakeholders and which helps converging faster (before the real implementation starts).
Magillem solution addresses all of these VP users and usages. We are the only IP-XACT based VP tool provider.
• an EDA independent environment (i.e. re-targetable from one EDA vendor to another),
• the ability to check before simulating (hence saving significant number of simulation runs),
• the capability to manage and analyze complex designs and configurations,
• the capability to import any legacy SystemC IP and connect to the major EDA VP tools and software debuggers
• the direct and straightforward link to the RTL design environment
Moreover, when coupling the Magillem VP solution with the Magillem traceability solution, one ends up with not just a product but a comprehensive solution to verify the System requirements and measure the impact of any change in real time.